Requirements :

- 10+ years of solid experience in SoC design.

- Experience with High Speed Protocol concepts.

- Experience with UFS/ Unipro IP/ MPHY/ sub-systems.

- MMC experience will be an added advantage.

- Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite.

- Good knowledge of Digital Design and RTL development.

Job Responsibilities :

- Hands-on experience with SoC Design, Verilog RTL coding.

- Working knowledge Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal -verification, silicon debug.

- Working knowledge of Lint CDC, VCLP, DFT, Power and Clock Flow.

- Good understanding of the design timing closure and verification debug.

- Manage SoC dependencies, planning and tracking of all front-end design related tasks.

- RTL Design: Develop and implement RTL code for various components of SoC designs, including datapaths, control logic, and interfaces.

- Microarchitecture Development: Contribute to the microarchitecture definition and optimization of SoC components to meet performance, area, and power targets.

- Synthesis and Timing Analysis: Work on logic synthesis, timing closure, and power optimization of RTL designs.

- Verification Collaboration: Collaborate with the verification team to develop test plans and ensure thorough validation of the design.

- Integration: Support the integration of RTL blocks into the larger SoC, ensuring proper connectivity and functionality.

- Design Reviews: Participate in design and code reviews to ensure design quality and adherence to best practices.

- Documentation: Create and maintain detailed design documentation for RTL blocks and SoC components.

- Debugging: Debug issues at various stages of the design flow, from RTL to :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field years of experience in RTL design for SoC architectures.

- Proficiency in hardware description languages such as Verilog or VHDL.

- Experience with EDA tools for synthesis, timing analysis, and simulation (e.g., Synopsys, Cadence).

- Strong understanding of digital design principles, including pipelining, clock domains, and low-power design techniques.

- Familiarity with high-level synthesis (HLS) and FPGA prototyping is a plus.

- Excellent problem-solving skills and attention to detail.

- Strong communication and teamwork abilities.

(ref:hirist.tech)

Global Employees

More Information